assignment editor quartus ii

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How to assign pins in Quartus II

We are looking at moving some code into a CPLD or FPGA in order to make it faster. I have worked with Xilinks and their suite of tools before, but for some reason it was decided that we'd use Altera this time around so I am trying to get used to Quartus II.

In particular, I am looking for a way to explicityly assign pins to the chip I am using. In Xilinx, I'd edit the netlist file but I can find no such thing in Quartus. There is a program (Assignments => Pin Planner) that does this, but it has a clunky GUI and I'd far prefer to edit the pins in a text editor, so my twofold question is

A: How do I find the file that stores the pin assignment? It's not listed under my files in the project navigator but the pins I've assigned in Pin Planner stay from session to session so they must be stored somewhere .

B: Is this a horrible idea?

IDE is Quartus II 10.1 Development kit is MAX II Development Board Language is VHDL

EDIT: Right now, I've run into the problem that I'm trying to interface with the Dev Kit through USB. I'm making a serial data receiver on it and have given it a Data In pin. The Dev Kit has a USB receiver so I'm trying to map din to whichever pin the USB connector is on. According to a file I have (rm_maxII-develop_board-rev1.pdf) the USB connector is on "Board Designation U13" but when I go into the Pin PLanner and try to assign that, there is no PIN_U13. I suspect this is an error in the pdf, rather than in Pin Planner but seing as I've never worked with Altera products before, I'm very confused.

• Ah, you posted here too. :-) I added answer at overmapped.com/questions/how-to-assign-pins-in-quartus-ii –  Prof. Falken Commented Apr 11, 2011 at 14:29
• I did - slightly before I read about Overmapped and figured that'd be a better place for it. What's your user name on Overmapped? I see no replies from Amigable Clark Kant over there. –  shieldfoss Commented Apr 12, 2011 at 9:14
• Jakob. It's here too if you look around hard enough. :-) –  Prof. Falken Commented Apr 12, 2011 at 9:26

A) You need to edit the *.qsf file, and add lines similar to the following:

B) While I will sometimes use the pin planner in the early stages of a design, I almost exclusively edit the qsf file directly when modifying pins, adding or removing VHDL files from the design, etc. To be completely safe, when making large changes (particularly to optimization or compiler settings) I will make sure Quartus is not running. I've been working this way with Quartus since it came out, and have not had any problems.

Once your design is compiled, you can refer to the *.pin file to see the final pinout for the FPGA. In particular, refer to the column indicating whether or not the pin is manually assigned, as any pins not specifically assigned to a location will change pretty much every time you recompile the chip (which is sub-optimal if you've already made a PCB! :).

• @medivh, that I don't know, please tell us where you found it. –  Prof. Falken Commented Apr 13, 2011 at 10:04

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Altera FPGA I/O weak pull ups

In altera FPGA documentation they make reference to a "I/O weak pullup" functionality.

I would like to use internal weak pull up instead of external pullups , avoiding a PCB modification.

It seems is possible to activate weak pull up for an I/O in quartus. But there is no information on how to activate it.

• \$\begingroup\$ In the Assignment Editor, set the weak pull-up assignment to ON to enable the on-chip pull-up resistor for the pin. \$\endgroup\$ –  Qiu Commented Jul 27, 2016 at 13:00

3 Answers 3

There are two ways of doing it.

1. Pin Planner

The first approach is in the Pin Planner tool. This is the GUI that allows you to select which pin goes where. From the main window with your project open, go to the Assignments menu and select Pin Planner (or press Ctrl + Shift + N ).

In the pin planner window, in the All pins view at the bottom, right click on any column header, and select "Customise Columns":

In the window that opens, scroll down in the left hand side and find "Weak Pull-up Resistor" (it's third one up from the bottom on mine). Click on that, then click the right arrow button to add it to the visible columns. Then click OK.

Now back in the Pin Planner window, you should see a new column called Weak Pull-Up Resistor. For each pin you wish to enable it on, simply click in the box for that column and select "On" (you can also type On into the box). By default it is turned "Off" - so if the column is blank, it means the same as if it says off.

2. Assignment Editor

You can also assign it manually with the "Assignment Editor" tool. This is useful if, say, you want to enable it for all pins in a bus, or even just all pins. You can use wildcards here.

Open the assignment editor tool in the main window by going to the "Assignments" menu and selecting "Assignment Editor" (or press Ctrl + Shift + A )

At the bottom of the list of assignments, there is a row where all entries are <<New>> . Click in the "Assignment Name" column and select "Weak Pull-Up Resistor". Then in the "Value" column, select "On". Finally in the "To" column, enter the pin name (which can include the wildcard character * ).

This will enable the pull-up for any pin matching the name in the "To" column.

• \$\begingroup\$ Fantastic answer! BTW, how weak is the weak pullup? Nevermind, just found it, it's 25kiloohms to Vccio: profesores.fi-b.unam.mx/maixx/Biblioteca/Librero_Computacion/… \$\endgroup\$ –  Eyal Commented Nov 13, 2016 at 13:07

I would like to point out that the weak pullup resistors on an FPGA/SOC/MCU are not a replacement for real external pullups. So when devising a strategy to use it please take the following into account.

• On-chip weak pullups are primarily for use when pins are left unused in a design and the pads do not have anything connected in the board etch artwork.
• The on-chip weak pullup resistors are typically in the range of 50K to 100K ohms. An input trace connected to such is susceptible to coupling from neighboring noisy traces due to the relative high impedance of the net.
• Circuit modes that operate in open drain or open collector mode will have lazy (slow) rise times due to the high resistance of weak pullups.
• External circuits that depend upon a pullup to bias an external component such as an NPN transistor will likely not get enough source current due to the high resistance of weak pullup resistors.
• Use of on-chip pullup resistors increases overall power consumption in a device when external circuits assert signal levels that counteract the pullups.
• Unused pins with an external component provide a connection point for testing and board design re-work.

So my recommendation is to follow the best known design methodology that has been adopted at many companies, large and small, and use external pullup resistors on nets that come off an FPGA/SOC/MCU for connection to other parts of the board or to test points. Design recommendations such as these suggest pullups no greater than 10K ohms be used with 4.7K being generally better. Smaller values to be selected where warranted by the circuit requirements.

Note that nearly all the same comments and recommendations apply to the use of on-chip weak pull down resistors too.

• \$\begingroup\$ Whom ever felt the need to downvote this answer has clearly never had real practical experience in high volume production electronics and the (a) variation of resistance value in silicon on chip resistors, (b) how high of resistance these on chip resistors really are, and (c) how susceptable circuits on boards that depend on only on on chip pullup/pulldown resistors are to upset due to real world electrical disturbances. \$\endgroup\$ –  Michael Karas Commented Mar 4, 2023 at 8:23

Within the qsf file, you can add the following: set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to pin_name

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Pin assignment does not show in graphic editor of Quartus II 16.1

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